update platine layout

This commit is contained in:
Robert Einsle 2017-01-29 18:39:04 +01:00
parent 18d0aa6d0a
commit 63edcab268
3 changed files with 3074 additions and 1752 deletions

598
adapter_platine.dsn Normal file
View File

@ -0,0 +1,598 @@
(pcb "C:\Users\reinsle\Documents\Sources\carom\carom-pcb\adapter_platine.dsn"
(parser
(string_quote ")
(space_in_quoted_tokens on)
(host_cad "KiCad's Pcbnew")
(host_version "4.0.5")
)
(resolution um 10)
(unit um)
(structure
(layer F.Cu
(type signal)
(property
(index 0)
)
)
(layer B.Cu
(type signal)
(property
(index 1)
)
)
(boundary
(rect pcb 91145 -53492 184545 -110425)
)
(plane GND (polygon B.Cu 0 184150 -109220 91440 -109220 91440 -66040 105410 -66040
105410 -54610 170180 -54610 170180 -66040 184150 -66040))
(via "Via[0-1]_600:400_um")
(rule
(width 250)
(clearance 200.1)
(clearance 200.1 (type default_smd))
(clearance 50 (type smd_smd))
)
)
(placement
(component "Housings_DIP:DIP-16_W7.62mm"
(place U2 152400 -77470 front 90 (PN PC847))
(place U1 105410 -77470 front 90 (PN PC847))
)
(component "Connectors:AK300-2"
(place P1 95250 -101600 front 0 (PN CONN_01X02))
(place P2 106680 -101600 front 0 (PN CONN_01X02))
(place P3 118110 -101600 front 0 (PN CONN_01X02))
(place P4 129540 -101600 front 0 (PN CONN_01X02))
(place P5 140970 -101600 front 0 (PN CONN_01X02))
(place P6 152400 -101600 front 0 (PN CONN_01X02))
(place P7 163830 -101600 front 0 (PN CONN_01X02))
(place P8 175260 -101600 front 0 (PN CONN_01X02))
)
(component Connectors:IDC_Header_Straight_40pins
(place P9 161290 -59690 front 180 (PN CONN_02X20))
)
(component Capacitors_THT:C_Disc_D3.0mm_W2.0mm_P2.50mm
(place C1 96520 -92710 front 0 (PN 0,1uF))
(place C2 107950 -92710 front 0 (PN 0,1uF))
(place C3 119380 -92710 front 0 (PN 0,1uF))
(place C4 130810 -92710 front 0 (PN 0,1uF))
(place C5 142240 -92710 front 0 (PN 0,1uF))
(place C6 153670 -92710 front 0 (PN 0,1uF))
(place C7 165100 -92710 front 0 (PN 0,1uF))
(place C8 176530 -92710 front 0 (PN 0,1uF))
)
(component LEDs:LED_D3.0mm
(place D1 97790 -85090 front 90 (PN LED))
(place D2 109220 -85090 front 90 (PN LED))
(place D3 120650 -85090 front 90 (PN LED))
(place D4 132080 -85090 front 90 (PN LED))
(place D5 143510 -85090 front 90 (PN LED))
(place D6 154940 -85090 front 90 (PN LED))
(place D7 166370 -85090 front 90 (PN LED))
(place D8 177800 -85090 front 90 (PN LED))
)
(component Resistors_THT:R_Axial_DIN0204_L3.6mm_D1.6mm_P7.62mm_Horizontal
(place R1 101600 -72390 front 180 (PN 10k))
(place R2 101600 -76200 front 180 (PN 10k))
(place R3 127000 -76200 front 0 (PN 10k))
(place R4 127000 -72390 front 0 (PN 10k))
(place R5 148590 -72390 front 180 (PN 10k))
(place R6 148590 -76200 front 180 (PN 10k))
(place R7 173990 -76200 front 0 (PN 10k))
(place R8 173990 -72390 front 0 (PN 10k))
(place R9 93980 -90170 front 90 (PN 270))
(place R10 105410 -90170 front 90 (PN 270))
(place R11 116840 -90170 front 90 (PN 270))
(place R12 128270 -90170 front 90 (PN 270))
(place R13 139700 -90170 front 90 (PN 270))
(place R14 151130 -90170 front 90 (PN 270))
(place R15 162560 -90170 front 90 (PN 270))
(place R16 173990 -90170 front 90 (PN 270))
(place R17 101600 -90170 front 90 (PN 220))
(place R18 113030 -90170 front 90 (PN 220))
(place R19 124460 -90170 front 90 (PN 220))
(place R20 135890 -90170 front 90 (PN 220))
(place R21 147320 -90170 front 90 (PN 270))
(place R22 158750 -90170 front 90 (PN 270))
(place R23 170180 -90170 front 90 (PN 270))
(place R24 181610 -90170 front 90 (PN 270))
)
)
(library
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(outline (path signal 100 1635 1270 6985 1270))
(outline (path signal 100 6985 1270 6985 -19050))
(outline (path signal 100 6985 -19050 635 -19050))
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(outline (path signal 50 -1100 -19300 8700 -19300))
(outline (path signal 50 8700 -19300 8700 1600))
(outline (path signal 50 8700 1600 -1100 1600))
(pin Rect[A]Pad_1600x1600_um 1 0 0)
(pin Oval[A]Pad_1600x1600_um 9 7620 -17780)
(pin Oval[A]Pad_1600x1600_um 2 0 -2540)
(pin Oval[A]Pad_1600x1600_um 10 7620 -15240)
(pin Oval[A]Pad_1600x1600_um 3 0 -5080)
(pin Oval[A]Pad_1600x1600_um 11 7620 -12700)
(pin Oval[A]Pad_1600x1600_um 4 0 -7620)
(pin Oval[A]Pad_1600x1600_um 12 7620 -10160)
(pin Oval[A]Pad_1600x1600_um 5 0 -10160)
(pin Oval[A]Pad_1600x1600_um 13 7620 -7620)
(pin Oval[A]Pad_1600x1600_um 6 0 -12700)
(pin Oval[A]Pad_1600x1600_um 14 7620 -5080)
(pin Oval[A]Pad_1600x1600_um 7 0 -15240)
(pin Oval[A]Pad_1600x1600_um 15 7620 -2540)
(pin Oval[A]Pad_1600x1600_um 8 0 -17780)
(pin Oval[A]Pad_1600x1600_um 16 7620 0)
)
(image "Connectors:AK300-2"
(outline (path signal 120 -2650 6300 -2650 -6300))
(outline (path signal 120 -2650 -6300 7700 -6300))
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(outline (path signal 100 3360 250 6670 250))
(pin Rect[A]Pad_1980x3960_um 1 0 0)
(pin Oval[A]Pad_1980x3960_um 2 5000 0)
)
(image Connectors:IDC_Header_Straight_40pins
(outline (path signal 100 -5080 5820 53340 5820))
(outline (path signal 100 -4540 5270 52780 5270))
(outline (path signal 100 -5080 -3280 53340 -3280))
(outline (path signal 100 -4540 -2730 21880 -2730))
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(outline (path signal 120 53590 6070 53590 -3530))
(outline (path signal 120 53590 -3530 -5330 -3530))
(outline (path signal 120 -5330 -3530 -5330 6070))
(pin Rect[A]Pad_1727.2x1727.2_um 1 0 0)
(pin Oval[A]Pad_1727.2x1727.2_um 2 0 2540)
(pin Oval[A]Pad_1727.2x1727.2_um 3 2540 0)
(pin Oval[A]Pad_1727.2x1727.2_um 4 2540 2540)
(pin Oval[A]Pad_1727.2x1727.2_um 5 5080 0)
(pin Oval[A]Pad_1727.2x1727.2_um 6 5080 2540)
(pin Oval[A]Pad_1727.2x1727.2_um 7 7620 0)
(pin Oval[A]Pad_1727.2x1727.2_um 8 7620 2540)
(pin Oval[A]Pad_1727.2x1727.2_um 9 10160 0)
(pin Oval[A]Pad_1727.2x1727.2_um 10 10160 2540)
(pin Oval[A]Pad_1727.2x1727.2_um 11 12700 0)
(pin Oval[A]Pad_1727.2x1727.2_um 12 12700 2540)
(pin Oval[A]Pad_1727.2x1727.2_um 13 15240 0)
(pin Oval[A]Pad_1727.2x1727.2_um 14 15240 2540)
(pin Oval[A]Pad_1727.2x1727.2_um 15 17780 0)
(pin Oval[A]Pad_1727.2x1727.2_um 16 17780 2540)
(pin Oval[A]Pad_1727.2x1727.2_um 17 20320 0)
(pin Oval[A]Pad_1727.2x1727.2_um 18 20320 2540)
(pin Oval[A]Pad_1727.2x1727.2_um 19 22860 0)
(pin Oval[A]Pad_1727.2x1727.2_um 20 22860 2540)
(pin Oval[A]Pad_1727.2x1727.2_um 21 25400 0)
(pin Oval[A]Pad_1727.2x1727.2_um 22 25400 2540)
(pin Oval[A]Pad_1727.2x1727.2_um 23 27940 0)
(pin Oval[A]Pad_1727.2x1727.2_um 24 27940 2540)
(pin Oval[A]Pad_1727.2x1727.2_um 25 30480 0)
(pin Oval[A]Pad_1727.2x1727.2_um 26 30480 2540)
(pin Oval[A]Pad_1727.2x1727.2_um 27 33020 0)
(pin Oval[A]Pad_1727.2x1727.2_um 28 33020 2540)
(pin Oval[A]Pad_1727.2x1727.2_um 29 35560 0)
(pin Oval[A]Pad_1727.2x1727.2_um 30 35560 2540)
(pin Oval[A]Pad_1727.2x1727.2_um 31 38100 0)
(pin Oval[A]Pad_1727.2x1727.2_um 32 38100 2540)
(pin Oval[A]Pad_1727.2x1727.2_um 33 40640 0)
(pin Oval[A]Pad_1727.2x1727.2_um 34 40640 2540)
(pin Oval[A]Pad_1727.2x1727.2_um 35 43180 0)
(pin Oval[A]Pad_1727.2x1727.2_um 36 43180 2540)
(pin Oval[A]Pad_1727.2x1727.2_um 37 45720 0)
(pin Oval[A]Pad_1727.2x1727.2_um 38 45720 2540)
(pin Oval[A]Pad_1727.2x1727.2_um 39 48260 0)
(pin Oval[A]Pad_1727.2x1727.2_um 40 48260 2540)
)
(image Capacitors_THT:C_Disc_D3.0mm_W2.0mm_P2.50mm
(outline (path signal 100 -250 1000 -250 -1000))
(outline (path signal 100 -250 -1000 2750 -1000))
(outline (path signal 100 2750 -1000 2750 1000))
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(outline (path signal 50 -1050 -1350 3550 -1350))
(outline (path signal 50 3550 -1350 3550 1350))
(outline (path signal 50 3550 1350 -1050 1350))
(pin Round[A]Pad_1600_um 1 0 0)
(pin Round[A]Pad_1600_um 2 2500 0)
)
(image LEDs:LED_D3.0mm
(outline (path signal 100 2770 0 2696.59 -463.525 2483.53 -881.678 2151.68 -1213.53
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(outline (path signal 120 -290 -1080 -290 -1236))
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(outline (path signal 50 -1150 -2250 3700 -2250))
(outline (path signal 50 3700 -2250 3700 2250))
(outline (path signal 50 3700 2250 -1150 2250))
(pin Rect[A]Pad_1800x1800_um 1 0 0)
(pin Round[A]Pad_1800_um 2 2540 0)
)
(image Resistors_THT:R_Axial_DIN0204_L3.6mm_D1.6mm_P7.62mm_Horizontal
(outline (path signal 100 2010 800 2010 -800))
(outline (path signal 100 2010 -800 5610 -800))
(outline (path signal 100 5610 -800 5610 800))
(outline (path signal 100 5610 800 2010 800))
(outline (path signal 100 0 0 2010 0))
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(outline (path signal 120 5670 -860 5670 860))
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(outline (path signal 50 -950 -1150 8600 -1150))
(outline (path signal 50 8600 -1150 8600 1150))
(outline (path signal 50 8600 1150 -950 1150))
(pin Round[A]Pad_1400_um 1 0 0)
(pin Oval[A]Pad_1400x1400_um 2 7620 0)
)
(padstack Round[A]Pad_1400_um
(shape (circle F.Cu 1400))
(shape (circle B.Cu 1400))
(attach off)
)
(padstack Round[A]Pad_1600_um
(shape (circle F.Cu 1600))
(shape (circle B.Cu 1600))
(attach off)
)
(padstack Round[A]Pad_1800_um
(shape (circle F.Cu 1800))
(shape (circle B.Cu 1800))
(attach off)
)
(padstack Oval[A]Pad_1400x1400_um
(shape (path F.Cu 1400 0 0 0 0))
(shape (path B.Cu 1400 0 0 0 0))
(attach off)
)
(padstack Oval[A]Pad_1600x1600_um
(shape (path F.Cu 1600 0 0 0 0))
(shape (path B.Cu 1600 0 0 0 0))
(attach off)
)
(padstack Oval[A]Pad_1727.2x1727.2_um
(shape (path F.Cu 1727.2 0 0 0 0))
(shape (path B.Cu 1727.2 0 0 0 0))
(attach off)
)
(padstack Oval[A]Pad_1980x3960_um
(shape (path F.Cu 1980 0 -990 0 990))
(shape (path B.Cu 1980 0 -990 0 990))
(attach off)
)
(padstack Rect[A]Pad_1600x1600_um
(shape (rect F.Cu -800 -800 800 800))
(shape (rect B.Cu -800 -800 800 800))
(attach off)
)
(padstack Rect[A]Pad_1727.2x1727.2_um
(shape (rect F.Cu -863.6 -863.6 863.6 863.6))
(shape (rect B.Cu -863.6 -863.6 863.6 863.6))
(attach off)
)
(padstack Rect[A]Pad_1800x1800_um
(shape (rect F.Cu -900 -900 900 900))
(shape (rect B.Cu -900 -900 900 900))
(attach off)
)
(padstack Rect[A]Pad_1980x3960_um
(shape (rect F.Cu -990 -1980 990 1980))
(shape (rect B.Cu -990 -1980 990 1980))
(attach off)
)
(padstack "Via[0-1]_600:400_um"
(shape (circle F.Cu 600))
(shape (circle B.Cu 600))
(attach off)
)
)
(network
(net +5V
(pins P1-1 P2-1 P3-1 P4-1 P5-1 P6-1 P7-1 P8-1 P9-2 P9-4 C1-1 C2-1 C3-1 C4-1
C5-1 C6-1 C7-1 C8-1)
)
(net "Net-(C1-Pad2)"
(pins P1-2 C1-2 R9-1 R17-1)
)
(net "Net-(C2-Pad2)"
(pins P2-2 C2-2 R10-1 R18-1)
)
(net "Net-(C3-Pad2)"
(pins P3-2 C3-2 R11-1 R19-1)
)
(net "Net-(C4-Pad2)"
(pins P4-2 C4-2 R12-1 R20-1)
)
(net "Net-(C5-Pad2)"
(pins P5-2 C5-2 R13-1 R21-1)
)
(net "Net-(C6-Pad2)"
(pins P6-2 C6-2 R14-1 R22-1)
)
(net "Net-(C7-Pad2)"
(pins P7-2 C7-2 R15-1 R23-1)
)
(net "Net-(C8-Pad2)"
(pins P8-2 C8-2 R16-1 R24-1)
)
(net GND
(pins U2-2 U2-4 U2-6 U2-8 P9-6 P9-9 P9-14 P9-20 P9-25 P9-30 P9-34 P9-39 U1-2
U1-4 U1-6 U1-8 D1-1 D2-1 D3-1 D4-1 D5-1 D6-1 D7-1 D8-1 R1-2 R2-2 R3-2 R4-2
R5-2 R6-2 R7-2 R8-2)
)
(net "Net-(D1-Pad2)"
(pins D1-2 R17-2)
)
(net "Net-(D2-Pad2)"
(pins D2-2 R18-2)
)
(net "Net-(D3-Pad2)"
(pins D3-2 R19-2)
)
(net "Net-(D4-Pad2)"
(pins D4-2 R20-2)
)
(net "Net-(D5-Pad2)"
(pins D5-2 R21-2)
)
(net "Net-(D6-Pad2)"
(pins D6-2 R22-2)
)
(net "Net-(D7-Pad2)"
(pins D7-2 R23-2)
)
(net "Net-(D8-Pad2)"
(pins D8-2 R24-2)
)
(net +3V3
(pins U2-10 U2-12 U2-14 U2-16 P9-1 P9-17 U1-10 U1-12 U1-14 U1-16)
)
(net "Net-(P9-Pad3)"
(pins P9-3)
)
(net "Net-(P9-Pad5)"
(pins P9-5)
)
(net "Net-(P9-Pad7)"
(pins P9-7)
)
(net "Net-(P9-Pad8)"
(pins P9-8)
)
(net "Net-(P9-Pad10)"
(pins P9-10)
)
(net "Net-(P9-Pad11)"
(pins P9-11)
)
(net "Net-(P9-Pad12)"
(pins P9-12)
)
(net "Net-(P9-Pad13)"
(pins P9-13)
)
(net "Net-(P9-Pad15)"
(pins P9-15)
)
(net "Net-(P9-Pad16)"
(pins U2-9 P9-16 R8-1)
)
(net "Net-(P9-Pad18)"
(pins U2-11 P9-18 R7-1)
)
(net "Net-(P9-Pad19)"
(pins P9-19)
)
(net "Net-(P9-Pad21)"
(pins P9-21)
)
(net "Net-(P9-Pad22)"
(pins U2-13 P9-22 R6-1)
)
(net "Net-(P9-Pad23)"
(pins P9-23)
)
(net "Net-(P9-Pad24)"
(pins U2-15 P9-24 R5-1)
)
(net "Net-(P9-Pad26)"
(pins P9-26 U1-9 R4-1)
)
(net "Net-(P9-Pad27)"
(pins P9-27)
)
(net "Net-(P9-Pad28)"
(pins P9-28)
)
(net "Net-(P9-Pad29)"
(pins P9-29)
)
(net "Net-(P9-Pad31)"
(pins P9-31)
)
(net "Net-(P9-Pad32)"
(pins P9-32 U1-11 R3-1)
)
(net "Net-(P9-Pad33)"
(pins P9-33)
)
(net "Net-(P9-Pad35)"
(pins P9-35)
)
(net "Net-(P9-Pad36)"
(pins P9-36 U1-13 R2-1)
)
(net "Net-(P9-Pad37)"
(pins P9-37)
)
(net "Net-(P9-Pad38)"
(pins P9-38 U1-15 R1-1)
)
(net "Net-(P9-Pad40)"
(pins P9-40)
)
(net "Net-(R9-Pad2)"
(pins U1-1 R9-2)
)
(net "Net-(R10-Pad2)"
(pins U1-3 R10-2)
)
(net "Net-(R11-Pad2)"
(pins U1-5 R11-2)
)
(net "Net-(R12-Pad2)"
(pins U1-7 R12-2)
)
(net "Net-(R13-Pad2)"
(pins U2-1 R13-2)
)
(net "Net-(R14-Pad2)"
(pins U2-3 R14-2)
)
(net "Net-(R15-Pad2)"
(pins U2-5 R15-2)
)
(net "Net-(R16-Pad2)"
(pins U2-7 R16-2)
)
(class kicad_default "" +3V3 +5V GND "Net-(C1-Pad2)" "Net-(C2-Pad2)" "Net-(C3-Pad2)"
"Net-(C4-Pad2)" "Net-(C5-Pad2)" "Net-(C6-Pad2)" "Net-(C7-Pad2)" "Net-(C8-Pad2)"
"Net-(D1-Pad2)" "Net-(D2-Pad2)" "Net-(D3-Pad2)" "Net-(D4-Pad2)" "Net-(D5-Pad2)"
"Net-(D6-Pad2)" "Net-(D7-Pad2)" "Net-(D8-Pad2)" "Net-(P9-Pad10)" "Net-(P9-Pad11)"
"Net-(P9-Pad12)" "Net-(P9-Pad13)" "Net-(P9-Pad15)" "Net-(P9-Pad16)"
"Net-(P9-Pad18)" "Net-(P9-Pad19)" "Net-(P9-Pad21)" "Net-(P9-Pad22)"
"Net-(P9-Pad23)" "Net-(P9-Pad24)" "Net-(P9-Pad26)" "Net-(P9-Pad27)"
"Net-(P9-Pad28)" "Net-(P9-Pad29)" "Net-(P9-Pad3)" "Net-(P9-Pad31)" "Net-(P9-Pad32)"
"Net-(P9-Pad33)" "Net-(P9-Pad35)" "Net-(P9-Pad36)" "Net-(P9-Pad37)"
"Net-(P9-Pad38)" "Net-(P9-Pad40)" "Net-(P9-Pad5)" "Net-(P9-Pad7)" "Net-(P9-Pad8)"
"Net-(R10-Pad2)" "Net-(R11-Pad2)" "Net-(R12-Pad2)" "Net-(R13-Pad2)"
"Net-(R14-Pad2)" "Net-(R15-Pad2)" "Net-(R16-Pad2)" "Net-(R9-Pad2)"
(circuit
(use_via Via[0-1]_600:400_um)
)
(rule
(width 250)
(clearance 200.1)
)
)
)
(wiring
)
)

File diff suppressed because it is too large Load Diff

File diff suppressed because it is too large Load Diff